Our premier client is seeking a Senior Physical Design Engineer to develop designs for AI/ML centric and CPU architectures. This role will involve performing Logic Equivalence Checks (LEC) to ensure functional consistency between RTL and gate-level netlists, along with debugging and resolving equivalence issues. This role will also work closely with front-end design teams and engage in physical design tasks such as synthesis, PnR, and timing closure. This is a hybrid role with possible locations in Silicon Valley and Austin, TX.
Responsibilities:
- Perform Logic Equivalence Check (LEC) to ensure functional consistency between RTL and gate-level netlists.
- Collaborate with front-end design teams to understand design specifications.
- Debug and resolve equivalence check issues, including formal verification failures and synthesis mismatches.
- Make recommendations to improve design flows and methodologies for LEC.
- Perform physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization.
- Utilize industry-standard EDA tools Synthesis, LEC, PnR, timing closure tasks.
Requirements:
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 5+ years of experience in physical design and verification.
- Solid understanding of digital design principles, RTL coding, and synthesis.
- Solid experience with synthesis, block and chip level implementation with industry standard PnR flows and tools.
- Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows.
- Proven communication and teamwork skills.
Immigration Requirements:
This role requires candidates to be a US Citizen or US Permanent Resident. This role will consider a H1-B transfer for a strong candidate currently residing in the United States.
Relocation Assistance:
This position will provide relocation assistance for the selected candidate.
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