Our premier Silicon Valley System-on-a Chip (SoC) startup client is seeking a Principal ASIC Design Engineer to architect and design an artificial intelligence (AI) chip to significantly reduce tapeout schedules. This unique AI chip design will accelerate future SoC designs across various AI domains. This pivotal role will be a part of an early staged startup that is on the cutting edge of AI/ML deep learning chip design that will transform a trillion dollar industry.
Note: All candidates MUST have at least 10 years of industry experience for this role. All candidates MUST currently live in the United States.
Responsibilities:
- Architect and lead RTL design and verification efforts that directly impact our AI-driven chip design platform.
- Take ownership of hardware evaluation frameworks and drive benchmarking initiatives.
- Work closely with ML engineers to translate hardware requirements into actionable specifications.
- Build and maintain hardware testing infrastructure that validates our AI-generated designs.
- Lead client conversations to understand hardware requirements and translate them for the technical team.
- Architect and implement hardware evaluation pipelines from requirements gathering to validation.
Requirements:
- MS or PhD in Electrical Engineering, Computer Engineering or related field.
- 10+ years of successful full chip design including: Architecting/Leading RTL designs in SystemVerilog for complex IP blocks; Chip Verification using UVM/ SystemVerilog verification methodology; and Physical Design – leading synthesis, floorplanning, P&R timing/physical verification on leading node tapeouts.
- Coding experience using Python, as well as writing scripts data pipelines around EDA flows.
- Hands-on with standard Synopsys/Cadence tools (Xcelium, Genus, Innovus, etc.) and associated TCL flows.
Preferred Experience:
- Prior work on AI-for-chip-design teams (e.g., Synopsys, Cadence, NVIDIA/AMD/Intel ML workflows) or DFT/power-optimization flow experience.
- Methodology/Flow experience, having built production systems that manage flow and handoff across several stages of design.
Immigration Requirements:
This role will consider a H1-B transfer for a strong candidate currently residing in the San Francisco Bay Area/Silicon Valley.
Compensation:
- $200K – $300K
- Considerable Startup Equity
- Medical/Dental/Vision Benefits
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