Principal Hardware Engineer (AI/Startup) – Silicon Valley

Our premier Silicon Valley AI startup client is hiring a Principal Hardware Engineer to take a leadership role in defining the board-level and rack-level power delivery architecture for our next-generation, multi-kilowatt AI server platforms. This critical position will own the end-to-end design of high-current power delivery paths to advanced SoCs.

Note: All candidates MUST have at least 10 years of experience PCB design experience. All candidates MUST be a US Citizen or US Green Card Holder, and reside in the San Francisco Bay/Silicon Valley Area.

Responsibilities:

• Architect and design board-level, server-level, and rack-level power delivery systems for high-power subsystems.
• Define power delivery network (PDN) topology, including VRMs, POLs, vertical and lateral power routing, and high-current interfaces.
• Perform component selection (VRMs, FETs, inductors, bulk caps, MLCCs, connectors, busbars) and create derating, margin, and reliability guidelines.
• Lead decoupling capacitor strategy across package and PCB layers to meet target impedance and transient response goals.
• Drive power integrity analysis (AC/DC, Z-target, transient, EMI/EMC) and validate designs through modeling, simulation, and lab measurement.
• Collaborate with mechanical and thermal teams to ensure high-current routing, cooling requirements, and system constraints are aligned.
• Partner with silicon and package engineering to co-design vertical PDN paths, including socket interfaces, pin/bump maps, and transient load profiles. Review and advise silicon design to improve power integrity.
• Develop test plans for PDN validation, transient load tests, impedance measurement, and system bring-up.
• Provide expertise during failure analysis, root-cause investigations, and corrective actions for system power issues.

Requirements:

• BS/MS in Electrical Engineering or related field.
• 10+ years of experience in high-power delivery design.
• Experience in server-class PCB design, including stackup planning, high-current routing, and decoupling strategies.
• Demonstrated experience designing high-current, low-voltage power delivery for SoCs.
• Deep expertise in power integrity, PDN modeling, VRM design, target impedance definition, and transient response optimization.
• Knowledge of rack-level power architectures, ORv3/OCP standards, power shelves, and busbar system
• Proficiency with SPICE, PDN simulation tools (Keysight, Cadence Sigrity/Clarity, Ansys SIwave), and measurement equipment (VNAs, oscilloscopes, electronic loads).
• Solid understanding of package-to-PCB PDN interactions.
• Strong communication and cross-functional collaboration skills.

Visa Requirements:

• All candidates MUST be a US Citizen or US Green Card Holder, and reside in the San Francisco Bay/Silicon Valley Area.

#pcb #AI #ML #hardwareengineering #server #datacenter #semiconductor #startup #hiring