Our premier Silicon Valley AI startup client is hiring a senior-level SoC Architect to lead the design and integration of their management subsystem within their AI acceleration platform. This role will be responsible for defining the SoC-level architecture for control and management flows — integrating ARM cores, interconnects, high-speed IO, and system management interfaces.
Note: All candidates MUST have at least 6 years of industry experience for this role. We are not currently accepting recent college graduates at this time. All candidates MUST currently live in the United States.
Responsibilities:
- Define and own the management subsystem architecture for our AI SoC.
- Integrate ARM cores (CSS/Cortex-A) and associated subsystems for control, configuration, and monitoring.
- Architect PCIe connectivity and high-bandwidth IO to ensure robust host and device communication.
- Specify and integrate DDR/LPDDR interfaces and memory management structures.
- Design peripheral and control interfaces, including SPI, I2C, UART, GPIO, and system control buses.
- Develop scheduler and interrupt schemes, driver-facing control paths, and configuration frameworks.
- Integrate and optimize debug and trace infrastructures (CoreSight, profilers, diagnostic tools).
- Collaborate with RTL, verification, firmware, and board teams to ensure seamless hardware-software co-design.
- Drive tradeoffs and decisions to achieve performance, power, and area targets across the SoC.
Requirements:
- Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or related field.
- 6+ years of experience in SoC architecture and design, with emphasis on management or control subsystems.
- Strong understanding of SoC design flows, memory hierarchy, and interconnect fabrics.
- Experience with AI/ML acceleration hardware or high-performance compute SoCs.
- Proven experience with ARM core integration, PCIe, DDR/LPDDR, and peripheral interfaces (SPI, I2C, UART).
- Knowledge of board-level integration and hardware-software co-validation.
- Familiarity with silicon prototyping, emulation, or FPGA-based validation.
- Strong understanding of SoC design flows, memory hierarchy, and interconnect fabrics.
- Hands-on experience in control path design, driver interfaces, and interrupt management.
- Solid communication and teamwork skills, with the ability to lead cross-functional architectural discussions.
Relocation and Visa Requirements:
- Strongly prefer candidates that reside in the San Francisco Bay Area/Silicon Valley Area.
- Will provide relocation assistance to the right candidate (that resides in the United States).
- Will transfer H1-B Visa to candidates (that resides in the United States).
- All candidates MUST reside in the United States.
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